1. Field of the Invention
The present invention relates to an analog-to-digital (A/D) converter, and more particularly, to an A/D converter with lower fabricating cost and improved reliability.
2. Discussion of the Related Art
Generally, A/D converters are divided into integrated types and comparison types. The A/D converter of the comparison type includes a feedback comparison type, which is representative of a successive-approximation type A/D converter, and a non-feedback comparison type, which is representative of a parallel comparison type A/D converter. The A/D converter of the successive-approximation type includes a digital-to-analog (D/A) converter and compares an input analog signal with an output of the D/A converter to have the output of the D/A converter coincide with an input analog signal.
FIG. 1 is a block diagram illustrating a conventional A/D converter of the successive-approximation type, FIG. 2 is a circuit diagram illustrating a comparator of a conventional A/D converter of the successive-approximation type, and FIG. 3 is a flow chart illustrating operation of the conventional A/D converter of the successive-approximation type.
As shown in FIG. 1, the conventional A/D converter of the successive-approximation type includes a sample-and-hold (S/H) circuit 11, a comparator 12, a successive-approximation register (SAR) 13, a D/A converter 14, a controller 15, and an output detector 16. The S/H circuit 11 samples and holds the input analog signal and outputs an input analog voltage V.sub.AN. The SAR 13 stores digital values of the comparator 12 and outputs a final digital value by inputting the output of the output detector 16. The D/A converter 14 receives a reference voltage Vref and the digital values of the SAR 13, and outputs a digital-to-analog voltage V.sub.D/A, which will be compared with V.sub.AN by decoding the digital values.
As shown in FIG. 2, the comparator 12 includes a first transfer gate 17 to which V.sub.AN is input, a second transfer gate 18 to which V.sub.D/A is input, a capacitor 19 to which the outputs of the first and second transfer gates 17 and 18 are input, a third transfer gate 20 to which the output of the capacitor 19 is input, and a CMOS inverter 21. The comparator 12 compares V.sub.D/A with V.sub.AN and outputs a digital value.
An operational amplifier whose negative (-) terminal is connected to V.sub.D/A and whose positive (+) terminal is connected to the output data of the S/H circuit 11 may also serve as the comparator 12.
The controller 15 outputs a clock signal and an enable signal to control operation of the A/D converter by inputting the output data from a register controlled by a user as well as the output data of the output detector 16.
The output detector 16 detects a conversion value of the lowest bit of the SAR 13 by inputting the digital values of the SAR 13, and outputs a conversion end signal.
If the conventional A/D converter of the successive-approximation type as described above is N-bit in hardware, the conversion time is N clock periods.
The operation of the conventional A/D converter of the successive-approximation type will be described with reference to FIG. 3. If all operations are controlled by the controller 15, it is assumed that the A/D converter is N bit, and V.sub.AN is in a verse 0-Vref. If the second transfer gate 18 is turned off, the S/H circuit 11 samples and holds V.sub.AN, and the comparator 12 is initiated.
During the first clock period, the A/D converter operates as follows:
The digital value of the SAR 13 is 100 . . . 000 (N-bits). This digital value is converted into V.sub.D/A, i.e, Vref/2, by the D/A converter 14 in step 100. If the comparator 12 compares V.sub.D/A with V.sub.AN in step 200, a high value or a low value is obtained. In other words, if the output of the comparator 12 is high, that is, V.sub.AN &lt;V.sub.D/A, the highest bit of the SAR 13 becomes "0" in step 300. If the output of the comparator 12 is low, that is, V.sub.AN &gt;V.sub.D/A, the highest bit of the SAR 13 becomes "1" in step 400.
When the output of the comparator 12 is low, the digital value of the SAR 13 is 100 . . . 000. V.sub.D/A is converted into Vref/2+Vref/4 by the D/A converter 14 in step 500. When the output of the comparator 12 is high, the digital value of the SAR 13 is 000 . . . 000. V.sub.D/A is converted into Vref/2-Vref/4 by the D/A converter 14 in step 600.
During the second clock period, the A/D converter operates as follows:
First, if the resulting value of the digital value of the SAR 13 in the first clock period is 100 . . . 000, the digital value of the SAR 13 becomes 110 . . . 000 and V.sub.D/A is Vref/2+Vref/4. The comparator 12 compares V.sub.D/A with V.sub.AN in step 200. As a result, a high value or a low value is obtained.
If the output of the comparator 12 is high, the digital value of the SAR 13 becomes 100 . . . 000. If the output of the comparator 12 is low, the digital value of the SAR 13 becomes 110 . . . 000.
Meanwhile, if the resulting value of the digital value of the SAR 13 in the first clock period is 000 . . . 000, the digital value of the SAR 13 becomes 010 . . . 000 and V.sub.D/A is Vref/2-Vref/4. The comparator 12 compares V.sub.D/A with V.sub.AN in step 200. As a result, a high value or a low value is obtained. If the output of the comparator 12 is high, the digital value of the SAR 13 is 000 . . . 000. If the output of the comparator 12 is low, the digital value of the SAR 13 is 010 . . . 000.
If the above steps are repeated N times in an N-bit A/D converter, the digital value of N bits can be obtained.
If (N+1)th clock period signal is generated in step 800, the conversion end signal is generated by the output detector 16 and the digital value is output by the SAR 13. Thus, the operation of the A/D converter ends.
The conventional A/D converter has a number of problems.
In the conventional A/D converter, the number of conversion bits is determined in hardware, the number of conversion operations required is equal to the number of conversion bits N and is defined by the hardware even if a smaller number of conversion bits is required. This increases conversion time, and increases a number of switching operations of the transfer gate which receives the output of the D/A converter, thereby causing charge injection. As a result, reliability of the A/D converter is reduced.